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jannaumarcan
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m1n1: hv: Use Apple implementation specific ACTLR_EL12 on M1*
Fixes: 99571e5 ("hv: Use architectural ACTLR_EL12 on M2+") Signed-off-by: Janne Grunau <[email protected]>
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Lines changed: 14 additions & 2 deletions

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proxyclient/m1n1/hv/__init__.py

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1441,9 +1441,13 @@ def init(self):
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self.map_vuart()
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actlr = ACTLR(self.u.mrs(ACTLR_EL12))
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# ACTLR depends on the CPU part
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part = MIDR(self.u.mrs(MIDR_EL1)).PART
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actlr_el12 = ACTLR_EL12 if part >= MIDR_PART.T8110_BLIZZARD else ACTLR_EL12_PRE
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actlr = ACTLR(self.u.mrs(actlr_el12))
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actlr.EnMDSB = 1
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self.u.msr(ACTLR_EL12, actlr.value)
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self.u.msr(actlr_el12, actlr.value)
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self.setup_adt()
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proxyclient/m1n1/sysreg.py

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -379,5 +379,13 @@ class TLBI_RVA(Register64):
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TTL = 38, 37
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BaseADDR = 36, 0
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class MIDR_PART(IntEnum):
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T8110_BLIZZARD = 0x30
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class MIDR(Register64):
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REV_LOW = 3, 0
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PART = 15, 4
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REV_HIGH = 23, 20
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__all__.extend(k for k, v in globals().items()
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if (callable(v) or isinstance(v, type)) and v.__module__ == __name__)

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