dart-t8110: flush/init

Signed-off-by: R <[email protected]>

Author: ArcaneNibble

proxyclient/m1n1/hw/dart8110.py

@@ -314,37 +314,37 @@ def get_pt(self, addr, uncached=False):
 
         return cached, self.pt_cache[addr]
 
-#     def flush_pt(self, addr):
-#         assert addr in self.pt_cache
-#         self.iface.writemem(addr, struct.pack(f"<{self.Lx_SIZE}Q", *self.pt_cache[addr]))
+    def flush_pt(self, addr):
+        assert addr in self.pt_cache
+        self.iface.writemem(addr, struct.pack(f"<{self.Lx_SIZE}Q", *self.pt_cache[addr]))
 
-#     def initialize(self):
-#         for i in range(15):
-#             self.regs.TCR[i].reg = R_TCR(TRANSLATE_ENABLE=1)
-#         self.regs.TCR[15].reg = R_TCR(BYPASS_DART=1)
+    def initialize(self):
+        for i in range(15):
+            self.regs.TCR[i].reg = R_TCR(TRANSLATE_ENABLE=1)
+        self.regs.TCR[15].reg = R_TCR(BYPASS_DART=1)
 
-#         for i in range(16):
-#             for j in range(4):
-#                 self.regs.TTBR[i, j].reg = R_TTBR(VALID = 0)
+        for i in range(16):
+            self.regs.TTBR[i].reg = R_TTBR(VALID = 0)
 
-#         self.regs.ERROR.val = 0xffffffff
-#         self.regs.UNK1.val = 0
-#         self.regs.ENABLED_STREAMS.val = 0
-#         self.enabled_streams = 0
+        # self.regs.ERROR.val = 0xffffffff
+        # self.regs.UNK1.val = 0
+        self.regs.DISABLE_STREAMS[0].val = 0xffff
+        self.enabled_streams = 0
 
-#         self.invalidate_streams()
+        self.invalidate_streams()
 
 #     def show_error(self):
 #         if self.regs.ERROR.reg.FLAG:
 #             print(f"ERROR: {self.regs.ERROR.reg!s}")
 #             print(f"ADDR: {self.regs.ERROR_ADDR_HI.val:#x}:{self.regs.ERROR_ADDR_LO.val:#x}")
 #             self.regs.ERROR.val = 0xffffffff
 
-#     def invalidate_streams(self, streams=0xffffffff):
-#         self.regs.STREAM_SELECT.val = streams
-#         self.regs.STREAM_COMMAND.val = R_STREAM_COMMAND(INVALIDATE=1)
-#         while self.regs.STREAM_COMMAND.reg.BUSY:
-#             pass
+    def invalidate_streams(self, streams=0xffff):
+        for sid in range(256):
+            if streams & (1 << sid):
+                self.regs.TLB_OP.val = R_TLB_OP(STREAM=sid, OP=1)
+                while self.regs.TLB_OP.reg.BUSY:
+                    pass
 
     def invalidate_cache(self):
         self.pt_cache = {}