chickens: Add T6021 chickens

Signed-off-by: Mario Hros <[email protected]>

Author: Mario Hros

src/chickens.c

@@ -18,6 +18,8 @@
 #define MIDR_PART_T8110_AVALANCHE 0x31
 #define MIDR_PART_T8112_BLIZZARD  0x32
 #define MIDR_PART_T8112_AVALANCHE 0x33
+#define MIDR_PART_T6021_BLIZZARD  0x38
+#define MIDR_PART_T6021_AVALANCHE 0x39
 
 #define MIDR_REV_LOW  GENMASK(3, 0)
 #define MIDR_PART     GENMASK(15, 4)
@@ -27,9 +29,10 @@ void init_m1_icestorm(void);
 void init_t8103_firestorm(int rev);
 void init_t6000_firestorm(int rev);
 void init_t6001_firestorm(int rev);
-
-void init_m2_blizzard(void);
+void init_t8112_blizzard(void);
 void init_t8112_avalanche(int rev);
+void init_t6021_blizzard(void);
+void init_t6021_avalanche(int rev);
 
 const char *init_cpu(void)
 {
@@ -87,7 +90,17 @@ const char *init_cpu(void)
 
         case MIDR_PART_T8112_BLIZZARD:
             cpu = "M2 Blizzard";
-            init_m2_blizzard();
+            init_t8112_blizzard();
+            break;
+
+        case MIDR_PART_T6021_AVALANCHE:
+            cpu = "M2 Max Avalanche";
+            init_t6021_avalanche(rev);
+            break;
+
+        case MIDR_PART_T6021_BLIZZARD:
+            cpu = "M2 Max Blizzard";
+            init_t6021_blizzard();
             break;
 
         default:

src/chickens_avalanche.c

@@ -32,8 +32,10 @@ static void init_common_avalanche(void)
     reg_mask(SYS_IMP_APL_HID27, HID27_GROUP3_OFFSET_MASK, HID27_GROUP3_OFFSET(31));
 }
 
-static void init_m2_avalanche(void)
+void init_t8112_avalanche(int rev)
 {
+    UNUSED(rev);
+
     init_common_avalanche();
 
     reg_mask(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_LIMIT_MASK, HID3_DEV_PCIE_THROTTLE_LIMIT(60));
@@ -42,9 +44,16 @@ static void init_m2_avalanche(void)
     reg_set(SYS_IMP_APL_HID16, HID16_AVL_UNK12);
 }
 
-void init_t8112_avalanche(int rev)
+void init_t6021_avalanche(int rev)
 {
     UNUSED(rev);
 
-    init_m2_avalanche();
+    init_common_avalanche();
+
+    reg_mask(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_LIMIT_MASK, HID3_DEV_PCIE_THROTTLE_LIMIT(62));
+    reg_set(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_ENABLE);
+    reg_set(SYS_IMP_APL_HID18, HID18_AVL_UNK27 | HID18_AVL_UNK29);
+    reg_set(SYS_IMP_APL_HID16, HID16_AVL_UNK12);
+
+    reg_mask(SYS_IMP_APL_HID5, HID5_BLZ_UNK_19_18_MASK, HID5_BLZ_UNK19);
 }

src/chickens_blizzard.c

@@ -8,11 +8,22 @@ static void init_common_blizzard(void)
     reg_set(SYS_IMP_APL_EHID0, EHID0_BLI_UNK32);
 }
 
-void init_m2_blizzard(void)
+void init_t8112_blizzard(void)
 {
     init_common_blizzard();
 
     reg_mask(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_LIMIT_MASK, EHID9_DEV_2_THROTTLE_LIMIT(60));
     reg_set(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_ENABLE);
     reg_set(SYS_IMP_APL_EHID18, EHID18_BLZ_UNK34);
 }
+
+void init_t6021_blizzard(void)
+{
+    init_common_blizzard();
+
+    reg_mask(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_LIMIT_MASK, EHID9_DEV_2_THROTTLE_LIMIT(62));
+    reg_set(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_ENABLE);
+    reg_set(SYS_IMP_APL_EHID18, EHID18_BLZ_UNK34);
+
+    reg_mask(SYS_IMP_APL_HID5, HID5_BLZ_UNK_19_18_MASK, HID5_BLZ_UNK19);
+}

src/cpu_regs.h

@@ -53,6 +53,9 @@
 #define HID4_ENABLE_LFSR_STALL_STQ_REPLAY        BIT(53)
 
 #define SYS_IMP_APL_HID5           sys_reg(3, 0, 15, 5, 0)
+#define HID5_BLZ_UNK_19_18_MASK    GENMASK(19, 18)
+#define HID5_BLZ_UNK18             BIT(18)
+#define HID5_BLZ_UNK19             BIT(19)
 #define HID5_DISABLE_FILL_2C_MERGE BIT(61)
 
 #define SYS_IMP_APL_HID6             sys_reg(3, 0, 15, 6, 0)