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ArcaneNibblemarcan
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dart-t8110: dump first-level translation tables
Signed-off-by: R <[email protected]>
1 parent 4a09eca commit 1602822

2 files changed

Lines changed: 33 additions & 34 deletions

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proxyclient/m1n1/hw/dart8110.py

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -305,14 +305,14 @@ def from_adt(cls, u, path):
305305

306306
# return ranges
307307

308-
# def get_pt(self, addr, uncached=False):
309-
# cached = True
310-
# if addr not in self.pt_cache or uncached:
311-
# cached = False
312-
# self.pt_cache[addr] = list(
313-
# struct.unpack(f"<{self.Lx_SIZE}Q", self.iface.readmem(addr, self.PAGE_SIZE)))
308+
def get_pt(self, addr, uncached=False):
309+
cached = True
310+
if addr not in self.pt_cache or uncached:
311+
cached = False
312+
self.pt_cache[addr] = list(
313+
struct.unpack(f"<{self.Lx_SIZE}Q", self.iface.readmem(addr, self.PAGE_SIZE)))
314314

315-
# return cached, self.pt_cache[addr]
315+
return cached, self.pt_cache[addr]
316316

317317
# def flush_pt(self, addr):
318318
# assert addr in self.pt_cache
@@ -392,33 +392,34 @@ def invalidate_cache(self):
392392
# if next_pte.VALID:
393393
# print_block(base, next_pte, start, 2048)
394394

395-
# def dump_table(self, base, l1_addr):
396-
# cached, tbl = self.get_pt(l1_addr)
395+
def dump_table(self, base, l1_addr):
396+
cached, tbl = self.get_pt(l1_addr)
397397

398-
# unmapped = False
399-
# for i, pte in enumerate(tbl):
400-
# pte = self.ptecls(pte)
401-
# if not pte.VALID:
402-
# if not unmapped:
403-
# print(" ...")
404-
# unmapped = True
405-
# continue
398+
unmapped = False
399+
for i, pte in enumerate(tbl):
400+
pte = PTE(pte)
401+
if not pte.VALID:
402+
if not unmapped:
403+
print(" ...")
404+
unmapped = True
405+
continue
406406

407-
# unmapped = False
407+
unmapped = False
408408

409-
# print(" table (%d): %08x ... %08x -> %016x [%d%d]" % (
410-
# i, base + i*0x2000000, base + (i+1)*0x2000000,
411-
# pte.OFFSET << self.PAGE_BITS, pte.SP_PROT_DIS, pte.VALID))
412-
# self.dump_table2(base + i*0x2000000, pte.OFFSET << self.PAGE_BITS)
409+
print(" table (%d): %09x ... %09x -> %016x [%d%d%d%d]" % (
410+
i, base + i*0x2000000, base + (i+1)*0x2000000,
411+
pte.OFFSET << self.PAGE_BITS,
412+
pte.RDPROT, pte.WRPROT, pte.UNCACHABLE, pte.VALID))
413+
# self.dump_table2(base + i*0x2000000, pte.OFFSET << self.PAGE_BITS)
413414

414-
# def dump_ttbr(self, idx, ttbr):
415-
# if not ttbr.VALID:
416-
# return
415+
def dump_ttbr(self, ttbr):
416+
if not ttbr.VALID:
417+
return
417418

418-
# l1_addr = (ttbr.ADDR) << 12
419-
# print(" TTBR%d: %09x" % (idx, l1_addr))
419+
l1_addr = (ttbr.ADDR) << self.PAGE_BITS
420+
print(" TTBR: %011x" % (l1_addr))
420421

421-
# self.dump_table(0, l1_addr)
422+
self.dump_table(0, l1_addr)
422423

423424
def dump_device(self, idx):
424425
tcr = self.regs.TCR[idx].reg
@@ -430,8 +431,7 @@ def dump_device(self, idx):
430431
elif tcr.TRANSLATE_ENABLE:
431432
print(" mode: TRANSLATE")
432433

433-
# for idx, ttbr in enumerate(ttbrs):
434-
# self.dump_ttbr(idx, ttbr.reg)
434+
self.dump_ttbr(ttbr.reg)
435435
elif tcr.BYPASS_DART:
436436
print(" mode: BYPASS")
437437
else:

proxyclient/m1n1/trace/dart8110.py

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
class DART8110Tracer(ADTDevTracer):
99
RELOAD_DEPS = [DART8110]
1010

11-
DEFAULT_MODE = TraceMode.ASYNC
11+
DEFAULT_MODE = TraceMode.SYNC
1212

1313
REGMAPS = [DART8110Regs]
1414
NAMES = ["regs"]
@@ -36,11 +36,10 @@ def w_TLB_OP(self, tlb_op):
3636
if tlb_op.OP == 0:
3737
self.log(f"Invalidate all")
3838
self.dart.invalidate_cache()
39+
self.dart.dump_all()
3940
elif tlb_op.OP == 1:
4041
self.log(f"Invalidate Stream: {tlb_op.STREAM}")
4142
self.dart.invalidate_cache()
43+
self.dart.dump_all()
4244
else:
4345
self.log(f"Unknown TLB op {tlb_op}")
44-
45-
def w_TTBR(self, ttbr, idx):
46-
self.dart.dump_all()

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