cpu_regs: Make fields usable from assembler

Signed-off-by: Hector Martin <[email protected]>

Author: marcan

src/cpu_regs.h

@@ -33,21 +33,21 @@
 #define HID1_ENABLE_BR_KILL_LIMIT           BIT(60)
 
 #define HID1_ZCL_RF_RESTART_THRESHOLD_MASK    GENMASK(23, 22)
-#define HID1_ZCL_RF_RESTART_THRESHOLD(x)      (((unsigned long)x) << 22)
+#define HID1_ZCL_RF_RESTART_THRESHOLD(x)      ((ULONG(x)) << 22)
 #define HID1_ZCL_RF_MISPREDICT_THRESHOLD_MASK GENMASK(43, 42)
-#define HID1_ZCL_RF_MISPREDICT_THRESHOLD(x)   (((unsigned long)x) << 42)
+#define HID1_ZCL_RF_MISPREDICT_THRESHOLD(x)   ((ULONG(x)) << 42)
 
 #define SYS_IMP_APL_HID3                  sys_reg(3, 0, 15, 3, 0)
 #define HID3_DISABLE_ARBITER_FIX_BIF_CRD  BIT(44)
 #define HID3_DEV_PCIE_THROTTLE_LIMIT_MASK GENMASK(62, 57)
-#define HID3_DEV_PCIE_THROTTLE_LIMIT(x)   (((unsigned long)x) << 57)
+#define HID3_DEV_PCIE_THROTTLE_LIMIT(x)   ((ULONG(x)) << 57)
 #define HID3_DEV_PCIE_THROTTLE_ENABLE     BIT(63)
 
 #define SYS_IMP_APL_HID4                         sys_reg(3, 0, 15, 4, 0)
 #define SYS_IMP_APL_EHID4                        sys_reg(3, 0, 15, 4, 1)
 #define HID4_DISABLE_DC_MVA                      BIT(11)
 #define HID4_DISABLE_DC_SW_L2_OPS                BIT(44)
-#define HID4_STNT_COUNTER_THRESHOLD(x)           (((unsigned long)x) << 40)
+#define HID4_STNT_COUNTER_THRESHOLD(x)           ((ULONG(x)) << 40)
 #define HID4_STNT_COUNTER_THRESHOLD_MASK         (3UL << 40)
 #define HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE BIT(49)
 #define HID4_ENABLE_LFSR_STALL_STQ_REPLAY        BIT(53)
@@ -59,13 +59,13 @@
 #define HID5_DISABLE_FILL_2C_MERGE BIT(61)
 
 #define SYS_IMP_APL_HID6             sys_reg(3, 0, 15, 6, 0)
-#define HID6_UP_CRD_TKN_INIT_C2(x)   (((unsigned long)x) << 5)
+#define HID6_UP_CRD_TKN_INIT_C2(x)   ((ULONG(x)) << 5)
 #define HID6_UP_CRD_TKN_INIT_C2_MASK (0x1FUL << 5)
 
 #define SYS_IMP_APL_HID7                                              sys_reg(3, 0, 15, 7, 0)
 #define HID7_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_INVALID_AND_MP_VALID BIT(16)
 #define HID7_FORCE_NONSPEC_IF_STEPPING                                BIT(20)
-#define HID7_FORCE_NONSPEC_TARGET_TIMER_SEL(x)                        (((unsigned long)x) << 24)
+#define HID7_FORCE_NONSPEC_TARGET_TIMER_SEL(x)                        ((ULONG(x)) << 24)
 #define HID7_FORCE_NONSPEC_TARGET_TIMER_SEL_MASK                      (3UL << 24)
 
 #define SYS_IMP_APL_HID9                sys_reg(3, 0, 15, 9, 0)
@@ -78,7 +78,7 @@
 #define SYS_IMP_APL_EHID9               sys_reg(3, 0, 15, 9, 1)
 #define EHID9_DEV_2_THROTTLE_ENABLE     BIT(5)
 #define EHID9_DEV_2_THROTTLE_LIMIT_MASK GENMASK(11, 6)
-#define EHID9_DEV_2_THROTTLE_LIMIT(x)   (((unsigned long)x) << 6)
+#define EHID9_DEV_2_THROTTLE_LIMIT(x)   ((ULONG(x)) << 6)
 
 #define SYS_IMP_APL_HID10               sys_reg(3, 0, 15, 10, 0)
 #define SYS_IMP_APL_EHID10              sys_reg(3, 0, 15, 10, 1)
@@ -90,27 +90,27 @@
 #define HID11_DISABLE_LD_NT_WIDGET   BIT(59)
 
 #define SYS_IMP_APL_HID13           sys_reg(3, 0, 15, 14, 0)
-#define HID13_POST_OFF_CYCLES(x)    (((unsigned long)x))
+#define HID13_POST_OFF_CYCLES(x)    ((ULONG(x)))
 #define HID13_POST_OFF_CYCLES_MASK  GENMASK(6, 0)
-#define HID13_POST_ON_CYCLES(x)     (((unsigned long)x) << 7)
+#define HID13_POST_ON_CYCLES(x)     ((ULONG(x)) << 7)
 #define HID13_POST_ON_CYCLES_MASK   GENMASK(13, 7)
-#define HID13_PRE_CYCLES(x)         (((unsigned long)x) << 14)
+#define HID13_PRE_CYCLES(x)         ((ULONG(x)) << 14)
 #define HID13_PRE_CYCLES_MASK       GENMASK(17, 14)
-#define HID13_GROUP0_FF1_DELAY(x)   (((unsigned long)x) << 26)
+#define HID13_GROUP0_FF1_DELAY(x)   ((ULONG(x)) << 26)
 #define HID13_GROUP0_FF1_DELAY_MASK GENMASK(29, 26)
-#define HID13_GROUP0_FF2_DELAY(x)   (((unsigned long)x) << 30)
+#define HID13_GROUP0_FF2_DELAY(x)   ((ULONG(x)) << 30)
 #define HID13_GROUP0_FF2_DELAY_MASK GENMASK(33, 30)
-#define HID13_GROUP0_FF3_DELAY(x)   (((unsigned long)x) << 34)
+#define HID13_GROUP0_FF3_DELAY(x)   ((ULONG(x)) << 34)
 #define HID13_GROUP0_FF3_DELAY_MASK GENMASK(37, 34)
-#define HID13_GROUP0_FF4_DELAY(x)   (((unsigned long)x) << 38)
+#define HID13_GROUP0_FF4_DELAY(x)   ((ULONG(x)) << 38)
 #define HID13_GROUP0_FF4_DELAY_MASK GENMASK(41, 38)
-#define HID13_GROUP0_FF5_DELAY(x)   (((unsigned long)x) << 42)
+#define HID13_GROUP0_FF5_DELAY(x)   ((ULONG(x)) << 42)
 #define HID13_GROUP0_FF5_DELAY_MASK GENMASK(45, 42)
-#define HID13_GROUP0_FF6_DELAY(x)   (((unsigned long)x) << 46)
+#define HID13_GROUP0_FF6_DELAY(x)   ((ULONG(x)) << 46)
 #define HID13_GROUP0_FF6_DELAY_MASK GENMASK(49, 46)
-#define HID13_GROUP0_FF7_DELAY(x)   (((unsigned long)x) << 50)
+#define HID13_GROUP0_FF7_DELAY(x)   ((ULONG(x)) << 50)
 #define HID13_GROUP0_FF7_DELAY_MASK GENMASK(53, 50)
-#define HID13_RESET_CYCLES(x)       (((unsigned long)x) << 60)
+#define HID13_RESET_CYCLES(x)       ((ULONG(x)) << 60)
 #define HID13_RESET_CYCLES_MASK     (0xFUL << 60)
 
 #define SYS_IMP_APL_HID14             sys_reg(3, 0, 15, 15, 0)
@@ -137,7 +137,7 @@
 #define EHID20_TRAP_SMC                                               BIT(8)
 #define EHID20_FORCE_NONSPEC_IF_OLDEST_REDIR_VALID_AND_OLDER          BIT(15)
 #define EHID20_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_NE_BLK_RTR_POINTER BIT(16)
-#define EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL(x)                    (((unsigned long)x) << 21)
+#define EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL(x)                    ((ULONG(x)) << 21)
 #define EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL_MASK                  (3UL << 21)
 
 #define SYS_IMP_APL_HID21                            sys_reg(3, 0, 15, 1, 3)
@@ -147,13 +147,13 @@
 #define HID21_AVL_UNK52                              BIT(52)
 
 #define SYS_IMP_APL_HID26        sys_reg(3, 0, 15, 0, 3)
-#define HID26_GROUP1_OFFSET(x)   (((unsigned long)x) << 0)
+#define HID26_GROUP1_OFFSET(x)   ((ULONG(x)) << 0)
 #define HID26_GROUP1_OFFSET_MASK (0xffUL << 0)
-#define HID26_GROUP2_OFFSET(x)   (((unsigned long)x) << 36)
+#define HID26_GROUP2_OFFSET(x)   ((ULONG(x)) << 36)
 #define HID26_GROUP2_OFFSET_MASK (0xffUL << 36)
 
 #define SYS_IMP_APL_HID27        sys_reg(3, 0, 15, 0, 4)
-#define HID27_GROUP3_OFFSET(x)   (((unsigned long)x) << 8)
+#define HID27_GROUP3_OFFSET(x)   ((ULONG(x)) << 8)
 #define HID27_GROUP3_OFFSET_MASK (0xffUL << 8)
 
 #define SYS_IMP_APL_PMCR0 sys_reg(3, 1, 15, 0, 0)
@@ -209,29 +209,29 @@
 
 /* ACC/CYC Registers */
 #define SYS_IMP_APL_ACC_CFG   sys_reg(3, 5, 15, 4, 0)
-#define ACC_CFG_BP_SLEEP(x)   (((unsigned long)x) << 2)
+#define ACC_CFG_BP_SLEEP(x)   ((ULONG(x)) << 2)
 #define ACC_CFG_BP_SLEEP_MASK (3UL << 2)
 
 #define SYS_IMP_APL_CYC_OVRD     sys_reg(3, 5, 15, 5, 0)
-#define CYC_OVRD_FIQ_MODE(x)     (((unsigned long)x) << 20)
+#define CYC_OVRD_FIQ_MODE(x)     ((ULONG(x)) << 20)
 #define CYC_OVRD_FIQ_MODE_MASK   (3UL << 20)
-#define CYC_OVRD_IRQ_MODE(x)     (((unsigned long)x) << 22)
+#define CYC_OVRD_IRQ_MODE(x)     ((ULONG(x)) << 22)
 #define CYC_OVRD_IRQ_MODE_MASK   (3UL << 22)
-#define CYC_OVRD_WFI_MODE(x)     (((unsigned long)x) << 24)
+#define CYC_OVRD_WFI_MODE(x)     ((ULONG(x)) << 24)
 #define CYC_OVRD_WFI_MODE_MASK   (3UL << 24)
 #define CYC_OVRD_DISABLE_WFI_RET BIT(0)
 
 #define SYS_IMP_APL_ACC_OVRD sys_reg(3, 5, 15, 6, 0)
 
-#define ACC_OVRD_PWR_DN_SRM(x)               (((unsigned long)x) << 13)
+#define ACC_OVRD_PWR_DN_SRM(x)               ((ULONG(x)) << 13)
 #define ACC_OVRD_PWR_DN_SRM_MASK             GENMASK(14, 13)
-#define ACC_OVRD_DIS_L2_FLUSH_ACC_SLEEP(x)   (((unsigned long)x) << 15)
+#define ACC_OVRD_DIS_L2_FLUSH_ACC_SLEEP(x)   ((ULONG(x)) << 15)
 #define ACC_OVRD_DIS_L2_FLUSH_ACC_SLEEP_MASK GENMASK(16, 15)
-#define ACC_OVRD_TRAIN_DOWN_LINK(x)          (((unsigned long)x) << 17)
+#define ACC_OVRD_TRAIN_DOWN_LINK(x)          ((ULONG(x)) << 17)
 #define ACC_OVRD_TRAIN_DOWN_LINK_MASK        GENMASK(18, 17)
-#define ACC_OVRD_POWER_DOWN_CPM(x)           (((unsigned long)x) << 25)
+#define ACC_OVRD_POWER_DOWN_CPM(x)           ((ULONG(x)) << 25)
 #define ACC_OVRD_POWER_DOWN_CPM_MASK         GENMASK(26, 25)
-#define ACC_OVRD_CPM_WAKE_UP(x)              (((unsigned long)x) << 27)
+#define ACC_OVRD_CPM_WAKE_UP(x)              ((ULONG(x)) << 27)
 #define ACC_OVRD_CPM_WAKE_UP_MASK            GENMASK(28, 27)
 #define ACC_OVRD_DISABLE_CLK_DTR             BIT(29)
 #define ACC_OVRD_DISABLE_PIO_ON_WFI_CPU      BIT(32)

src/types.h

@@ -49,12 +49,21 @@ typedef s64 ssize_t;
 #define SZ_1M  (1 << 20)
 #define SZ_32M (1 << 25)
 
+#define BIT(x)                 (1UL << (x))
+#define MASK(x)                (BIT(x) - 1)
+#define GENMASK(msb, lsb)      ((BIT((msb + 1) - (lsb)) - 1) << (lsb))
+#define _FIELD_LSB(field)      ((field) & ~(field - 1))
+#define FIELD_PREP(field, val) ((val) * (_FIELD_LSB(field)))
+#define FIELD_GET(field, val)  (((val) & (field)) / _FIELD_LSB(field))
+
 #ifdef __ASSEMBLER__
 
+#define ULONG(x)                         (x)
 #define sys_reg(op0, op1, CRn, CRm, op2) s##op0##_##op1##_c##CRn##_c##CRm##_##op2
 
 #else
 
+#define ULONG(x)                         ((unsigned long)(x))
 #define sys_reg(op0, op1, CRn, CRm, op2) , _S, op0, op1, CRn, CRm, op2
 
 #endif

src/utils.h

@@ -17,13 +17,6 @@
 
 #define ARRAY_SIZE(s) (sizeof(s) / sizeof((s)[0]))
 
-#define BIT(x)                 (1UL << (x))
-#define MASK(x)                (BIT(x) - 1)
-#define GENMASK(msb, lsb)      ((BIT((msb + 1) - (lsb)) - 1) << (lsb))
-#define _FIELD_LSB(field)      ((field) & ~(field - 1))
-#define FIELD_PREP(field, val) ((val) * (_FIELD_LSB(field)))
-#define FIELD_GET(field, val)  (((val) & (field)) / _FIELD_LSB(field))
-
 #define ALIGN_UP(x, a)   (((x) + ((a)-1)) & ~((a)-1))
 #define ALIGN_DOWN(x, a) ((x) & ~((a)-1))
 

src/utils_asm.S

@@ -154,7 +154,7 @@ put_simd_state:
 .type deep_wfi, @function
 deep_wfi:
     mrs x0, SYS_IMP_APL_CYC_OVRD
-    orr x1, x0, #(3L << 24)
+    orr x1, x0, #CYC_OVRD_WFI_MODE(3)
     msr SYS_IMP_APL_CYC_OVRD, x1
 
     stp x30, x0, [sp, #-16]!