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ArcaneNibblemarcan
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dart-t8110: fill in more details from poking
Signed-off-by: R <[email protected]>
1 parent 96b2d58 commit 0f6991c

1 file changed

Lines changed: 30 additions & 19 deletions

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proxyclient/m1n1/hw/dart8110.py

Lines changed: 30 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,6 @@ class R_PARAMS_C(Register32):
3939
NUM_SIDS = 8, 0
4040

4141
class R_ERROR(Register32):
42-
# bit31 unk
4342
FLAG = 31
4443
SMMU = 30
4544
REGION_PROTECT = 29
@@ -88,9 +87,9 @@ class R_TLB_OP_IDX(Register32):
8887
class R_PROTECT(Register32):
8988
LOCK_TZ_SELECT = 4
9089
LOCK_TZ_CONFIG = 3
91-
# These bits can be set, but unknown what they protect
90+
# This bit can be set, but unknown what it protects
9291
_BIT2 = 2
93-
_BIT1 = 1
92+
LOCK_REG_4xx = 1
9493
LOCK_TCR_TTBR = 0
9594

9695
class R_DIAG_LOCK(Register32):
@@ -124,7 +123,7 @@ class DART8110Regs(RegMap):
124123
PARAMS_4 = 0x004, R_PARAMS_4
125124
PARAMS_8 = 0x008, R_PARAMS_8
126125
PARAMS_C = 0x00C, R_PARAMS_C
127-
126+
# Unknown RO
128127
REG_0x10 = 0x010, Register32
129128
REG_0x14 = 0x014, Register32 # hwrev 2 only
130129

@@ -137,20 +136,23 @@ class DART8110Regs(RegMap):
137136
TLB_START_DVA_PAGE = 0x098, Register32 # hwrev 2 only
138137
TLB_END_DVA_PAGE = 0x0a0, Register32 # hwrev 2 only
139138

140-
ERROR = 0x100, R_ERROR
141-
REG_0x104 = 0x100, Register32
139+
ERROR = 0x100, R_ERROR
140+
# completely guessed, unverified
141+
# based on what bits can be set/cleared in it
142+
ERR_INTR_ENABLE = 0x104, Register32
143+
144+
# Found via register bruteforcing
145+
STREAM_UNK_SET = irange(0x120, 8, 4), Register32
146+
STREAM_UNK_CLR = irange(0x140, 8, 4), Register32
142147

143-
# 0x160, 0x180, 0x1a0 all accessed by interrupt handler
148+
# these are all accessed by error interrupt handler
144149
REG_0x160 = 0x160, Register32
145150
REG_0x164 = 0x164, Register32
146151
ERROR_ADDR_LO = 0x170, Register32
147152
ERROR_ADDR_HI = 0x174, Register32
148153
REG_0x178 = 0x178, Register32 # hwrev 2 only
149-
150154
REG_0x180 = irange(0x180, 4, 4), Register32
151-
152155
REG_0x1a0 = irange(0x1a0, 8, 4), Register32
153-
154156
ERR_SECONDARY = irange(0x1c0, 8, 4), Register32
155157

156158
# Write bits to _PROTECT to protect them.
@@ -160,16 +162,24 @@ class DART8110Regs(RegMap):
160162
REG_UNPROTECT = 0x204, R_PROTECT
161163
REG_PROTECT_LOCK = 0x208, R_PROTECT
162164

163-
REG_0x20c = 0x20c, Register32 # Tunables touch this
165+
# Tunables touch this, can set bits FF00001F, RW
166+
REG_0x20c = 0x20c, Register32
164167

165168
DIAG_LOCK = 0x210, R_DIAG_LOCK
166169

167-
# Unknown
170+
# All unknown, related to transaction queueing???
171+
172+
# can set bits 3FFFFFFC, RW
168173
REG_0x218 = 0x218, Register32
169-
REG_0x220 = 0x220, Register32 # Tunables touch this
170-
REG_0x224 = 0x224, Register32 # Tunables touch this
174+
# Tunables touch this, can set bits 000F0F0F, RW
175+
REG_0x220 = 0x220, Register32
176+
# Tunables touch this, can set bits 00FFFFFF, RW
177+
REG_0x224 = 0x224, Register32
178+
# can set bits 3F3F3F3F
171179
TLIMIT = 0x228, Register32
180+
# can set bits 07070707
172181
TEQRESERVE = 0x22c, Register32
182+
# RO, outstanding transaction count???
173183
TRANS = irange(0x230, 4, 4), Register32
174184

175185
# hwrev 2 only for all of these
@@ -187,10 +197,10 @@ class DART8110Regs(RegMap):
187197
REG_0x358 = 0x358, Register32
188198

189199
# Unknown
190-
REG_0x400 = 0x400, Register32
191-
REG_0x404 = 0x404, Register32
192-
REG_0x408 = 0x408, Register32
193-
REG_0x410 = 0x410, Register32
200+
REG_0x400 = 0x400, Register32 # can set 00000003
201+
REG_0x404 = 0x404, Register32 # can set 001FFFFF
202+
REG_0x408 = 0x408, Register32 # can set 00FFFFFC
203+
REG_0x410 = 0x410, Register32 # can set 3FFFFFFC
194204

195205
# These registers exist even though it's "not supported"
196206
TZ_CONFIG = 0x500, Register32 # 3 bits
@@ -205,7 +215,8 @@ class DART8110Regs(RegMap):
205215
TZ_REGION2_END = 0x540, Register32
206216
TZ_REGION2_OFFSET = 0x548, Register32
207217

208-
PERF_INTR_ENABLE = 0x700, Register32 # guessed
218+
# completely guessed, unverified, can set bits 0F077077
219+
PERF_INTR_ENABLE = 0x700, Register32
209220
PERF_INTR_STATUS = 0x704, Register32
210221

211222
PERF_UNK1 = irange(0x720, 8, 4), Register32

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