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experiments/cpu_pstate_latencies.py: Fix SoC configs
Signed-off-by: Hector Martin <[email protected]>
1 parent dabad98 commit 06884b5

1 file changed

Lines changed: 6 additions & 3 deletions

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proxyclient/experiments/cpu_pstate_latencies.py

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,21 +17,24 @@
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chip_id = u.adt["/chosen"].chip_id
1919

20-
if chip_id == 0x8103:
20+
if chip_id in (0x8103, 0x6000, 0x6001, 0x6002):
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CREG = [
2222
0x210e00000,
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0x211e00000,
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]
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MAX_PSTATE = [5, 15]
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elif chip_id == 0x8112 or chip_id == 0x6021:
28+
elif chip_id in (0x8121, 0x6020, 0x6021, 0x6022):
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CREG = [
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0x210e00000,
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0x211e00000,
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]
3333

34-
MAX_PSTATE = [7, 17]
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if chip_id == 0x8112:
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MAX_PSTATE = [7, 17]
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else:
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MAX_PSTATE = [7, 19]
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code = u.malloc(0x1000)
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