drm: apple: Add preliminary VRR support

DCP supports VRR/Adaptive Sync, with its enormous firmware blob
handling the low-level details for us. Display refresh rate is
determined by the swap timing values provided to DCP on each
swap request.

VRR is activated by setting IOMFBadaptive_sync_parameter::minRR
and then requesting a modeset.

Wire up all of the required KMS properties to expose VRR to
userspace, and tell DCP to enable it when supported. This
enables VRR *unconditionally* for supported sinks, which will
be fixed in a future commit.

Signed-off-by: James Calligeros <[email protected]>

Author: chadmed

drivers/gpu/drm/apple/apple_drv.c

@@ -335,6 +335,10 @@ static int apple_probe_per_dcp(struct device *dev,
 	if (ret)
 		return ret;
 
+	ret = drm_connector_attach_vrr_capable_property(&connector->base);
+	if (ret)
+		return ret;
+
 	connector->base.polled = DRM_CONNECTOR_POLL_HPD;
 	connector->connected = false;
 	connector->dcp = dcp;

drivers/gpu/drm/apple/iomfb.c

@@ -244,6 +244,7 @@ void dcp_hotplug(struct work_struct *work)
 
 	if (!connector->connected) {
 		drm_edid_free(connector->drm_edid);
+		drm_connector_set_vrr_capable_property(&connector->base, false);
 		connector->drm_edid = NULL;
 	}
 

drivers/gpu/drm/apple/iomfb_template.c

@@ -546,8 +546,9 @@ static u8 dcpep_cb_prop_chunk(struct apple_dcp *dcp,
 static bool dcpep_process_chunks(struct apple_dcp *dcp,
 				 struct dcp_set_dcpav_prop_end_req *req)
 {
+	struct apple_connector *connector = dcp->connector;
 	struct dcp_parse_ctx ctx;
-	int ret;
+	int ret, i;
 
 	if (!dcp->chunks.data) {
 		dev_warn(dcp->dev, "ignoring spurious end\n");
@@ -589,6 +590,15 @@ static bool dcpep_process_chunks(struct apple_dcp *dcp,
 		dcp_set_dimensions(dcp);
 	}
 
+	if (connector) {
+		for (i = 0; i < dcp->nr_modes; i++) {
+			if (dcp->modes[i].vrr) {
+				drm_connector_set_vrr_capable_property(&connector->base, true);
+				break;
+			}
+		}
+	}
+
 	return true;
 }
 
@@ -1171,6 +1181,33 @@ static void complete_set_digital_out_mode(struct apple_dcp *dcp, void *data,
 	}
 }
 
+/* Changes to Adaptive Sync require a trip through set_digital_out_mode */
+static void dcp_on_set_adaptive_sync(struct apple_dcp *dcp, void *out, void *cookie)
+{
+	dcp_set_digital_out_mode(dcp, false, &dcp->mode,
+				 complete_set_digital_out_mode, cookie);
+}
+
+static void dcp_set_adaptive_sync(struct apple_dcp *dcp, u32 rate, void *cookie)
+{
+	struct dcp_set_parameter_dcp param = {
+		.param = IOMFBPARAM_ADAPTIVE_SYNC,
+		.value = {
+			rate,              /* minRR */
+			0,                 /* mediaTargetRate */
+			0,                 /* Fractional Rate (?) */
+			0,                 /* unused */
+		},
+#if DCP_FW_VER >= DCP_FW_VERSION(13, 2, 0)
+		.count = 3,
+#else
+		.count = 1,
+#endif
+	};
+
+	dcp_set_parameter_dcp(dcp, false, &param, dcp_on_set_adaptive_sync, cookie);
+}
+
 int DCP_FW_NAME(iomfb_modeset)(struct apple_dcp *dcp,
 			       struct drm_crtc_state *crtc_state)
 {
@@ -1225,8 +1262,11 @@ int DCP_FW_NAME(iomfb_modeset)(struct apple_dcp *dcp,
 
 	dcp->during_modeset = true;
 
-	dcp_set_digital_out_mode(dcp, false, &dcp->mode,
-				 complete_set_digital_out_mode, cookie);
+	if (mode->vrr)
+		dcp_set_adaptive_sync(dcp, mode->min_vrr, cookie);
+	else
+		dcp_set_digital_out_mode(dcp, false, &dcp->mode,
+					 complete_set_digital_out_mode, cookie);
 
 	/*
 	 * The DCP firmware has an internal timeout of ~8 seconds for

drivers/gpu/drm/apple/parser.c

@@ -194,6 +194,26 @@ static int parse_int(struct dcp_parse_ctx *handle, s64 *value)
 	return 0;
 }
 
+/*
+ * DCP stores VRR refresh rates in 64-bit regions, however the number is actually an
+ * unsigned Q16.16 with the high 32 bits unused.
+ */
+static int parse_q1616(struct dcp_parse_ctx *handle, u32 *value)
+{
+	s64 dcp_int;
+	u32 in;
+	int ret;
+
+	ret = parse_int(handle, &dcp_int);
+	if (ret)
+		return ret;
+
+	in = dcp_int & 0xffffffff;
+
+	memcpy(value, &in, sizeof(*value));
+	return 0;
+}
+
 static int parse_bool(struct dcp_parse_ctx *handle, bool *b)
 {
 	const struct dcp_parse_tag *tag = parse_tag_of_type(handle, DCP_TYPE_BOOL);
@@ -454,6 +474,10 @@ static int parse_mode(struct dcp_parse_ctx *handle,
 			ret = parse_dimension(it.handle, &horiz);
 		else if (!strcmp(key, "VerticalAttributes"))
 			ret = parse_dimension(it.handle, &vert);
+		else if (!strcmp(key, "MinimumVariableRefreshRate"))
+			ret = parse_q1616(it.handle, &out->min_vrr);
+		else if (!strcmp(key, "MaximumVariableRefreshRate"))
+			ret = parse_q1616(it.handle, &out->max_vrr);
 		else if (!strcmp(key, "ColorModes"))
 			ret = parse_color_modes(it.handle, out);
 		else if (!strcmp(key, "ID"))
@@ -502,15 +526,17 @@ static int parse_mode(struct dcp_parse_ctx *handle,
 	/*
 	* HACK:
 	* Mark the 120 Hz mode on j314/j316 (identified by resolution) as vrr.
-	* We still do not know how to drive VRR but at least seetinng timestamps
-	* in the the swap_surface message to non-zero values drives the display
-	* at 120 fps.
+	* Setting timestamps in the the swap_surface message to non-zero
+	* values drives the display at 120 fps.
 	*/
 	if (vert.precise_sync_rate >> 16 == 120 &&
 	    ((horiz.active == 3024 && vert.active == 1964) ||
 	     (horiz.active == 3456 && vert.active == 2234)))
 		out->vrr = true;
 
+	if (out->min_vrr && out->max_vrr)
+		out->vrr = true;
+
 	vert.active -= notch_height;
 	vert.sync_width += notch_height;
 

drivers/gpu/drm/apple/parser.h

@@ -92,6 +92,8 @@ struct dcp_display_mode {
 	struct dcp_color_mode sdr;
 	struct dcp_color_mode best;
 	bool vrr;
+	u32 min_vrr;
+	u32 max_vrr;
 };
 
 struct dimension {