drm/asahi: buffer,render: Identify and provide layer meta buf

It looks like one of the "heapmeta" pointers is actually a layer
metadata pointer, that macOS just allocates contiguously with the
tilemap headers and heap meta buffers. Size seems to always be 0x100.

Let's allocate it after the heapmeta, which will make debugging easier.

Signed-off-by: Asahi Lina <[email protected]>

Author: hoshinolina

drivers/gpu/drm/asahi/buffer.rs

@@ -91,6 +91,8 @@ pub(crate) struct TileInfo {
     pub(crate) tpc_size: usize,
     /// Number of blocks in the clustering meta buffer (for clustering).
     pub(crate) meta1_blocks: u32,
+    /// Layering metadata size.
+    pub(crate) layermeta_size: usize,
     /// Minimum number of TVB blocks for this render.
     pub(crate) min_tvb_blocks: usize,
     /// Tiling parameter structure passed to firmware.
@@ -163,6 +165,11 @@ impl Scene::ver {
         self.object.tvb_heapmeta.gpu_pointer()
     }
 
+    /// Returns the GPU pointer to the layer metadata buffer.
+    pub(crate) fn tvb_layermeta_pointer(&self) -> GpuPointer<'_, &'_ [u8]> {
+        self.object.tvb_heapmeta.gpu_offset_pointer(0x200)
+    }
+
     /// Returns the GPU pointer to the top-level TVB tilemap buffer.
     pub(crate) fn tvb_tilemap_pointer(&self) -> GpuPointer<'_, &'_ [u8]> {
         self.object.tvb_tilemap.gpu_pointer()
@@ -546,7 +553,10 @@ impl Buffer::ver {
             b"UBUF",
         )?;
 
-        let tvb_heapmeta = inner.ualloc.lock().array_empty_tagged(0x200, b"HMTA")?;
+        let tvb_heapmeta = inner
+            .ualloc
+            .lock()
+            .array_empty_tagged(0x200 + tile_info.layermeta_size, b"HMTA")?;
         let tvb_tilemap = inner
             .ualloc
             .lock()

drivers/gpu/drm/asahi/fw/fragment.rs

@@ -97,9 +97,9 @@ pub(crate) mod raw {
         pub(crate) stencil_meta_buffer_ptr2: U64,
         pub(crate) unk_d0: U64,
         pub(crate) tvb_tilemap: GpuPointer<'a, &'a [u8]>,
-        pub(crate) tvb_heapmeta: GpuPointer<'a, &'a [u8]>,
+        pub(crate) tvb_layermeta: GpuPointer<'a, &'a [u8]>,
         pub(crate) mtile_stride_dwords: U64,
-        pub(crate) tvb_heapmeta_2: GpuPointer<'a, &'a [u8]>,
+        pub(crate) tvb_heapmeta: GpuPointer<'a, &'a [u8]>,
         pub(crate) tile_config: U64,
         pub(crate) aux_fb: GpuPointer<'a, &'a [u8]>,
         pub(crate) unk_108: Array<0x6, U64>,

drivers/gpu/drm/asahi/fw/vertex.rs

@@ -47,7 +47,7 @@ pub(crate) mod raw {
         pub(crate) utile_config: u32,
         pub(crate) unk_4c: u32,
         pub(crate) ppp_multisamplectl: U64,
-        pub(crate) tvb_heapmeta_2: GpuPointer<'a, &'a [u8]>,
+        pub(crate) tvb_layermeta: GpuPointer<'a, &'a [u8]>,
         #[ver(G < G14)]
         pub(crate) unk_60: U64,
         #[ver(G < G14)]

drivers/gpu/drm/asahi/queue/render.rs

@@ -168,6 +168,7 @@ impl super::Queue::ver {
             tilemap_size,
             tpc_size,
             meta1_blocks,
+            layermeta_size: if layers > 1 { 0x100 } else { 0 },
             min_tvb_blocks: min_tvb_blocks as usize,
             params: fw::vertex::raw::TilingParameters {
                 rgn_size,
@@ -797,9 +798,9 @@ impl super::Queue::ver {
                         stencil_meta_buffer_ptr2: U64(cmdbuf.stencil_meta_buffer_store),
                         unk_d0: Default::default(),
                         tvb_tilemap: inner.scene.tvb_tilemap_pointer(),
-                        tvb_heapmeta: inner.scene.tvb_heapmeta_pointer(),
+                        tvb_layermeta: inner.scene.tvb_layermeta_pointer(),
                         mtile_stride_dwords: U64((4 * tile_info.params.rgn_size as u64) << 24),
-                        tvb_heapmeta_2: inner.scene.tvb_heapmeta_pointer(),
+                        tvb_heapmeta: inner.scene.tvb_heapmeta_pointer(),
                         tile_config: U64(tile_config),
                         aux_fb: inner.aux_fb.gpu_pointer(),
                         unk_108: Default::default(),
@@ -899,7 +900,7 @@ impl super::Queue::ver {
                             r.add(0x153d9, cmdbuf.stencil_meta_buffer_store);
                             r.add(0x15439, 0);
                             r.add(0x16429, inner.scene.tvb_tilemap_pointer().into());
-                            r.add(0x16060, inner.scene.tvb_heapmeta_pointer().into());
+                            r.add(0x16060, inner.scene.tvb_layermeta_pointer().into());
                             r.add(0x16431, (4 * tile_info.params.rgn_size as u64) << 24); // ISP_RGN?
                             r.add(0x10039, tile_config); // tile_config ISP_CTL?
                             r.add(0x16451, 0x0); // ISP_RENDER_ORIGIN
@@ -1281,7 +1282,7 @@ impl super::Queue::ver {
                         utile_config,
                         unk_4c: 0,
                         ppp_multisamplectl: U64(cmdbuf.ppp_multisamplectl), // fixed
-                        tvb_heapmeta_2: inner.scene.tvb_heapmeta_pointer(),
+                        tvb_layermeta: inner.scene.tvb_layermeta_pointer(),
                         #[ver(G < G14)]
                         unk_60: U64(0x0), // fixed
                         #[ver(G < G14)]
@@ -1371,8 +1372,8 @@ impl super::Queue::ver {
                             ); // tvb_cluster_meta3
                             r.add(0x1c890, tiling_control.into()); // tvb_tiling_control
                             r.add(0x1c918, unks.tiling_control_2);
-                            r.add(0x1c079, inner.scene.tvb_heapmeta_pointer().into());
-                            r.add(0x1c9d8, inner.scene.tvb_heapmeta_pointer().into());
+                            r.add(0x1c079, inner.scene.tvb_layermeta_pointer().into());
+                            r.add(0x1c9d8, inner.scene.tvb_layermeta_pointer().into());
                             r.add(0x1c089, 0);
                             r.add(0x1c9e0, 0);
                             let cl_meta_4_pointer =