drm/i915/snps_hdmi_pll: Fix 64-bit divisor truncation by using div64_u64

DIV_ROUND_CLOSEST_ULL uses do_div(), which expects a 32-bit divisor.
When passing a 64-bit constant like CURVE2_MULTIPLIER, the value is
silently truncated to u32, potentially leading to incorrect results
on large divisors.

Replace DIV_ROUND_CLOSEST_ULL with DIV64_U64_ROUND_CLOSEST which correctly
handles full 64-bit division.

v2: Use DIV64_U64_ROUND_CLOSEST instead of div64_u64 macro. (Jani)

Fixes: 5947642 ("drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2")
Reported-by: Vas Novikov <[email protected]>
Closes: https://lore.kernel.org/all/[email protected]/
Cc: Ankit Nautiyal <[email protected]>
Cc: Suraj Kandpal <[email protected]>
Cc: Jani Nikula <[email protected]>
Cc: Vas Novikov <[email protected]>
Cc: [email protected] # v6.15+
Reviewed-by: Jani Nikula <[email protected]>
Signed-off-by: Ankit Nautiyal <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
(cherry picked from commit b300a17)
Signed-off-by: Joonas Lahtinen <[email protected]>

Author: aknautiyal

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

@@ -103,8 +103,8 @@ static void get_ana_cp_int_prop(u64 vco_clk,
 			    DIV_ROUND_DOWN_ULL(curve_1_interpolated, CURVE0_MULTIPLIER)));
 
 	ana_cp_int_temp =
-		DIV_ROUND_CLOSEST_ULL(DIV_ROUND_DOWN_ULL(adjusted_vco_clk1, curve_2_scaled1),
-				      CURVE2_MULTIPLIER);
+		DIV64_U64_ROUND_CLOSEST(DIV_ROUND_DOWN_ULL(adjusted_vco_clk1, curve_2_scaled1),
+					CURVE2_MULTIPLIER);
 
 	*ana_cp_int = max(1, min(ana_cp_int_temp, 127));