riscv: Update MIPS vendor id to 0x127

[1] defines MIPS vendor id as 0x127. All previous MIPS RISC-V patches
were tested on QEMU, also modified to use 0x722 as MIPS_VENDOR_ID. This
new value should reflect real hardware.

[1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf

Fixes: a8fed1b ("riscv: Add xmipsexectl as a vendor extension")
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Aleksa Paunovic <[email protected]>
Link: https://patch.msgid.link/[email protected]
Cc: <[email protected]>
Signed-off-by: Paul WAlmsley <[email protected]>

Author: icebergfu

arch/riscv/include/asm/vendorid_list.h

@@ -7,8 +7,8 @@
 
 #define ANDES_VENDOR_ID		0x31e
 #define MICROCHIP_VENDOR_ID	0x029
+#define MIPS_VENDOR_ID		0x127
 #define SIFIVE_VENDOR_ID	0x489
 #define THEAD_VENDOR_ID		0x5b7
-#define MIPS_VENDOR_ID		0x722
 
 #endif