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torvaldstorvalds
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Merge tag 'drm-fixes-2025-06-28' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Regular weekly drm updates, nothing out of the ordinary, amdgpu, xe, i915 and a few misc bits. Seems about right for this time in the release cycle. core: - fix drm_writeback_connector_cleanup function signature - use correct HDMI audio bridge in drm_connector_hdmi_audio_init bridge: - SN65DSI86: fix HPD amdgpu: - Cleaner shader support for additional GFX9 GPUs - MES firmware compatibility fixes - Discovery error reporting fixes - SDMA6/7 userq fixes - Backlight fix - EDID sanity check i915: - Fix for SNPS PHY HDMI for 1080p@120Hz - Correct DP AUX DPCD probe address - Followup build fix for GCOV and AutoFDO enabled config xe: - Missing error check - Fix xe_hwmon_power_max_write - Move flushes - Explicitly exit CT safe mode on unwind - Process deferred GGTT node removals on device unwind" * tag 'drm-fixes-2025-06-28' of https://gitlab.freedesktop.org/drm/kernel: drm/xe: Process deferred GGTT node removals on device unwind drm/xe/guc: Explicitly exit CT safe mode on unwind drm/xe: move DPT l2 flush to a more sensible place drm/xe: Move DSB l2 flush to a more sensible place drm/bridge: ti-sn65dsi86: Add HPD for DisplayPort connector type drm/i915: fix build error some more drm/xe/hwmon: Fix xe_hwmon_power_max_write drm/xe/display: Add check for alloc_ordered_workqueue() drm/amd/display: Add sanity checks for drm_edid_raw() drm/amd/display: Fix AMDGPU_MAX_BL_LEVEL value drm/amdgpu/sdma7: add ucode version checks for userq support drm/amdgpu/sdma6: add ucode version checks for userq support drm/amd: Adjust output for discovery error handling drm/amdgpu/mes: add compatibility checks for set_hw_resource_1 drm/amdgpu/gfx9: Add Cleaner Shader Support for GFX9.x GPUs drm/bridge-connector: Fix bridge in drm_connector_hdmi_audio_init() drm/dp: Change AUX DPCD probe address from DPCD_REV to LANE0_1_STATUS drm/i915/snps_hdmi_pll: Fix 64-bit divisor truncation by using div64_u64 drm: writeback: Fix drm_writeback_connector_cleanup signature
2 parents 26fd9f7 + 9fbceb3 commit 7abdafd

21 files changed

Lines changed: 189 additions & 81 deletions

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c‎

Lines changed: 13 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -321,10 +321,12 @@ static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev,
321321
const struct firmware *fw;
322322
int r;
323323

324-
r = request_firmware(&fw, fw_name, adev->dev);
324+
r = firmware_request_nowarn(&fw, fw_name, adev->dev);
325325
if (r) {
326-
dev_err(adev->dev, "can't load firmware \"%s\"\n",
327-
fw_name);
326+
if (amdgpu_discovery == 2)
327+
dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name);
328+
else
329+
drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name);
328330
return r;
329331
}
330332

@@ -459,16 +461,12 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)
459461
/* Read from file if it is the preferred option */
460462
fw_name = amdgpu_discovery_get_fw_name(adev);
461463
if (fw_name != NULL) {
462-
dev_info(adev->dev, "use ip discovery information from file");
464+
drm_dbg(&adev->ddev, "use ip discovery information from file");
463465
r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin, fw_name);
464-
465-
if (r) {
466-
dev_err(adev->dev, "failed to read ip discovery binary from file\n");
467-
r = -EINVAL;
466+
if (r)
468467
goto out;
469-
}
470-
471468
} else {
469+
drm_dbg(&adev->ddev, "use ip discovery information from memory");
472470
r = amdgpu_discovery_read_binary_from_mem(
473471
adev, adev->mman.discovery_bin);
474472
if (r)
@@ -1338,10 +1336,8 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
13381336
int r;
13391337

13401338
r = amdgpu_discovery_init(adev);
1341-
if (r) {
1342-
DRM_ERROR("amdgpu_discovery_init failed\n");
1339+
if (r)
13431340
return r;
1344-
}
13451341

13461342
wafl_ver = 0;
13471343
adev->gfx.xcc_mask = 0;
@@ -2579,8 +2575,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
25792575
break;
25802576
default:
25812577
r = amdgpu_discovery_reg_base_init(adev);
2582-
if (r)
2583-
return -EINVAL;
2578+
if (r) {
2579+
drm_err(&adev->ddev, "discovery failed: %d\n", r);
2580+
return r;
2581+
}
25842582

25852583
amdgpu_discovery_harvest_ip(adev);
25862584
amdgpu_discovery_get_gfx_info(adev);

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2235,6 +2235,25 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block)
22352235
}
22362236

22372237
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2238+
case IP_VERSION(9, 0, 1):
2239+
case IP_VERSION(9, 2, 1):
2240+
case IP_VERSION(9, 4, 0):
2241+
case IP_VERSION(9, 2, 2):
2242+
case IP_VERSION(9, 1, 0):
2243+
case IP_VERSION(9, 3, 0):
2244+
adev->gfx.cleaner_shader_ptr = gfx_9_4_2_cleaner_shader_hex;
2245+
adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_2_cleaner_shader_hex);
2246+
if (adev->gfx.me_fw_version >= 167 &&
2247+
adev->gfx.pfp_fw_version >= 196 &&
2248+
adev->gfx.mec_fw_version >= 474) {
2249+
adev->gfx.enable_cleaner_shader = true;
2250+
r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
2251+
if (r) {
2252+
adev->gfx.enable_cleaner_shader = false;
2253+
dev_err(adev->dev, "Failed to initialize cleaner shader\n");
2254+
}
2255+
}
2256+
break;
22382257
case IP_VERSION(9, 4, 2):
22392258
adev->gfx.cleaner_shader_ptr = gfx_9_4_2_cleaner_shader_hex;
22402259
adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_2_cleaner_shader_hex);

‎drivers/gpu/drm/amd/amdgpu/mes_v11_0.c‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1630,10 +1630,12 @@ static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
16301630
if (r)
16311631
goto failure;
16321632

1633-
r = mes_v11_0_set_hw_resources_1(&adev->mes);
1634-
if (r) {
1635-
DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);
1636-
goto failure;
1633+
if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x50) {
1634+
r = mes_v11_0_set_hw_resources_1(&adev->mes);
1635+
if (r) {
1636+
DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);
1637+
goto failure;
1638+
}
16371639
}
16381640

16391641
r = mes_v11_0_query_sched_status(&adev->mes);

‎drivers/gpu/drm/amd/amdgpu/mes_v12_0.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1742,7 +1742,8 @@ static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
17421742
if (r)
17431743
goto failure;
17441744

1745-
mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1745+
if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x4b)
1746+
mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE);
17461747

17471748
mes_v12_0_init_aggregated_doorbell(&adev->mes);
17481749

‎drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c‎

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1374,9 +1374,22 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
13741374
else
13751375
DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
13761376

1377-
/* add firmware version checks here */
1378-
if (0 && !adev->sdma.disable_uq)
1379-
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
1377+
switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1378+
case IP_VERSION(6, 0, 0):
1379+
if ((adev->sdma.instance[0].fw_version >= 24) && !adev->sdma.disable_uq)
1380+
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
1381+
break;
1382+
case IP_VERSION(6, 0, 2):
1383+
if ((adev->sdma.instance[0].fw_version >= 21) && !adev->sdma.disable_uq)
1384+
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
1385+
break;
1386+
case IP_VERSION(6, 0, 3):
1387+
if ((adev->sdma.instance[0].fw_version >= 25) && !adev->sdma.disable_uq)
1388+
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
1389+
break;
1390+
default:
1391+
break;
1392+
}
13801393

13811394
r = amdgpu_sdma_sysfs_reset_mask_init(adev);
13821395
if (r)

‎drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1349,9 +1349,15 @@ static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
13491349
else
13501350
DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
13511351

1352-
/* add firmware version checks here */
1353-
if (0 && !adev->sdma.disable_uq)
1354-
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
1352+
switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1353+
case IP_VERSION(7, 0, 0):
1354+
case IP_VERSION(7, 0, 1):
1355+
if ((adev->sdma.instance[0].fw_version >= 7836028) && !adev->sdma.disable_uq)
1356+
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
1357+
break;
1358+
default:
1359+
break;
1360+
}
13551361

13561362
return r;
13571363
}

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4718,16 +4718,16 @@ static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
47184718
return 1;
47194719
}
47204720

4721-
/* Rescale from [min..max] to [0..AMDGPU_MAX_BL_LEVEL] */
4721+
/* Rescale from [min..max] to [0..MAX_BACKLIGHT_LEVEL] */
47224722
static inline u32 scale_input_to_fw(int min, int max, u64 input)
47234723
{
4724-
return DIV_ROUND_CLOSEST_ULL(input * AMDGPU_MAX_BL_LEVEL, max - min);
4724+
return DIV_ROUND_CLOSEST_ULL(input * MAX_BACKLIGHT_LEVEL, max - min);
47254725
}
47264726

4727-
/* Rescale from [0..AMDGPU_MAX_BL_LEVEL] to [min..max] */
4727+
/* Rescale from [0..MAX_BACKLIGHT_LEVEL] to [min..max] */
47284728
static inline u32 scale_fw_to_input(int min, int max, u64 input)
47294729
{
4730-
return min + DIV_ROUND_CLOSEST_ULL(input * (max - min), AMDGPU_MAX_BL_LEVEL);
4730+
return min + DIV_ROUND_CLOSEST_ULL(input * (max - min), MAX_BACKLIGHT_LEVEL);
47314731
}
47324732

47334733
static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *caps,
@@ -4947,7 +4947,7 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
49474947
drm_dbg(drm, "Backlight caps: min: %d, max: %d, ac %d, dc %d\n", min, max,
49484948
caps->ac_level, caps->dc_level);
49494949
} else
4950-
props.brightness = props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4950+
props.brightness = props.max_brightness = MAX_BACKLIGHT_LEVEL;
49514951

49524952
if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE))
49534953
drm_info(drm, "Using custom brightness curve\n");

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1029,6 +1029,10 @@ enum dc_edid_status dm_helpers_read_local_edid(
10291029
return EDID_NO_RESPONSE;
10301030

10311031
edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
1032+
if (!edid ||
1033+
edid->extensions >= sizeof(sink->dc_edid.raw_edid) / EDID_LENGTH)
1034+
return EDID_BAD_INPUT;
1035+
10321036
sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
10331037
memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
10341038

‎drivers/gpu/drm/bridge/ti-sn65dsi86.c‎

Lines changed: 60 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -348,12 +348,18 @@ static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata,
348348
* 200 ms. We'll assume that the panel driver will have the hardcoded
349349
* delay in its prepare and always disable HPD.
350350
*
351-
* If HPD somehow makes sense on some future panel we'll have to
352-
* change this to be conditional on someone specifying that HPD should
353-
* be used.
351+
* For DisplayPort bridge type, we need HPD. So we use the bridge type
352+
* to conditionally disable HPD.
353+
* NOTE: The bridge type is set in ti_sn_bridge_probe() but enable_comms()
354+
* can be called before. So for DisplayPort, HPD will be enabled once
355+
* bridge type is set. We are using bridge type instead of "no-hpd"
356+
* property because it is not used properly in devicetree description
357+
* and hence is unreliable.
354358
*/
355-
regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
356-
HPD_DISABLE);
359+
360+
if (pdata->bridge.type != DRM_MODE_CONNECTOR_DisplayPort)
361+
regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
362+
HPD_DISABLE);
357363

358364
pdata->comms_enabled = true;
359365

@@ -1195,9 +1201,14 @@ static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge)
11951201
struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
11961202
int val = 0;
11971203

1198-
pm_runtime_get_sync(pdata->dev);
1204+
/*
1205+
* Runtime reference is grabbed in ti_sn_bridge_hpd_enable()
1206+
* as the chip won't report HPD just after being powered on.
1207+
* HPD_DEBOUNCED_STATE reflects correct state only after the
1208+
* debounce time (~100-400 ms).
1209+
*/
1210+
11991211
regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val);
1200-
pm_runtime_put_autosuspend(pdata->dev);
12011212

12021213
return val & HPD_DEBOUNCED_STATE ? connector_status_connected
12031214
: connector_status_disconnected;
@@ -1220,6 +1231,26 @@ static void ti_sn65dsi86_debugfs_init(struct drm_bridge *bridge, struct dentry *
12201231
debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
12211232
}
12221233

1234+
static void ti_sn_bridge_hpd_enable(struct drm_bridge *bridge)
1235+
{
1236+
struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1237+
1238+
/*
1239+
* Device needs to be powered on before reading the HPD state
1240+
* for reliable hpd detection in ti_sn_bridge_detect() due to
1241+
* the high debounce time.
1242+
*/
1243+
1244+
pm_runtime_get_sync(pdata->dev);
1245+
}
1246+
1247+
static void ti_sn_bridge_hpd_disable(struct drm_bridge *bridge)
1248+
{
1249+
struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1250+
1251+
pm_runtime_put_autosuspend(pdata->dev);
1252+
}
1253+
12231254
static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
12241255
.attach = ti_sn_bridge_attach,
12251256
.detach = ti_sn_bridge_detach,
@@ -1234,6 +1265,8 @@ static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
12341265
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
12351266
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
12361267
.debugfs_init = ti_sn65dsi86_debugfs_init,
1268+
.hpd_enable = ti_sn_bridge_hpd_enable,
1269+
.hpd_disable = ti_sn_bridge_hpd_disable,
12371270
};
12381271

12391272
static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
@@ -1321,8 +1354,26 @@ static int ti_sn_bridge_probe(struct auxiliary_device *adev,
13211354
pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort
13221355
? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP;
13231356

1324-
if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort)
1325-
pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
1357+
if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) {
1358+
pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT |
1359+
DRM_BRIDGE_OP_HPD;
1360+
/*
1361+
* If comms were already enabled they would have been enabled
1362+
* with the wrong value of HPD_DISABLE. Update it now. Comms
1363+
* could be enabled if anyone is holding a pm_runtime reference
1364+
* (like if a GPIO is in use). Note that in most cases nobody
1365+
* is doing AUX channel xfers before the bridge is added so
1366+
* HPD doesn't _really_ matter then. The only exception is in
1367+
* the eDP case where the panel wants to read the EDID before
1368+
* the bridge is added. We always consistently have HPD disabled
1369+
* for eDP.
1370+
*/
1371+
mutex_lock(&pdata->comms_mutex);
1372+
if (pdata->comms_enabled)
1373+
regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG,
1374+
HPD_DISABLE, 0);
1375+
mutex_unlock(&pdata->comms_mutex);
1376+
};
13261377

13271378
drm_bridge_add(&pdata->bridge);
13281379

‎drivers/gpu/drm/display/drm_bridge_connector.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -708,11 +708,14 @@ struct drm_connector *drm_bridge_connector_init(struct drm_device *drm,
708708
if (bridge_connector->bridge_hdmi_audio ||
709709
bridge_connector->bridge_dp_audio) {
710710
struct device *dev;
711+
struct drm_bridge *bridge;
711712

712713
if (bridge_connector->bridge_hdmi_audio)
713-
dev = bridge_connector->bridge_hdmi_audio->hdmi_audio_dev;
714+
bridge = bridge_connector->bridge_hdmi_audio;
714715
else
715-
dev = bridge_connector->bridge_dp_audio->hdmi_audio_dev;
716+
bridge = bridge_connector->bridge_dp_audio;
717+
718+
dev = bridge->hdmi_audio_dev;
716719

717720
ret = drm_connector_hdmi_audio_init(connector, dev,
718721
&drm_bridge_connector_hdmi_audio_funcs,

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