drm/asahi: Convert more ranges to Range<>

hoshinolina · hoshinolina · commit 1c5466037550 · 2024-05-10T21:06:48.000+09:00
Signed-off-by: Asahi Lina &lt;lina@asahilina.net&gt;
diff --git a/drivers/gpu/drm/asahi/alloc.rs b/drivers/gpu/drm/asahi/alloc.rs
@@ -19,13 +19,15 @@ use crate::driver::{AsahiDevRef, AsahiDevice};
 use crate::fw::types::Zeroable;
 use crate::mmu;
 use crate::object::{GpuArray, GpuObject, GpuOnlyArray, GpuStruct, GpuWeakPointer};
+use crate::util::RangeExt;
 
 use core::cmp::Ordering;
 use core::fmt;
 use core::fmt::{Debug, Formatter};
 use core::marker::PhantomData;
 use core::mem;
 use core::mem::MaybeUninit;
+use core::ops::Range;
 use core::ptr::NonNull;
 
 const DEBUG_CLASS: DebugFlags = DebugFlags::Alloc;
@@ -491,8 +493,7 @@ impl RawAllocation for SimpleAllocation {
 /// GPU's idea of object size what we expect.
 pub(crate) struct SimpleAllocator {
     dev: AsahiDevRef,
-    start: u64,
-    end: u64,
+    range: Range<u64>,
     prot: u32,
     vm: mmu::Vm,
     min_align: usize,
@@ -506,8 +507,7 @@ impl SimpleAllocator {
     pub(crate) fn new(
         dev: &AsahiDevice,
         vm: &mmu::Vm,
-        start: u64,
-        end: u64,
+        range: Range<u64>,
         min_align: usize,
         prot: u32,
         _block_size: usize,
@@ -521,8 +521,7 @@ impl SimpleAllocator {
         Ok(SimpleAllocator {
             dev: dev.into(),
             vm: vm.clone(),
-            start,
-            end,
+            range,
             prot,
             min_align,
             cpu_maps,
@@ -567,8 +566,7 @@ impl Allocator for SimpleAllocator {
         }
         let mapping = obj.map_into_range(
             &self.vm,
-            self.start,
-            self.end,
+            self.range.clone(),
             self.min_align.max(mmu::UAT_PGSZ) as u64,
             self.prot,
             true,
@@ -709,8 +707,7 @@ struct HeapAllocatorInner {
 /// never shrinks it.
 pub(crate) struct HeapAllocator {
     dev: AsahiDevRef,
-    start: u64,
-    end: u64,
+    range: Range<u64>,
     top: u64,
     prot: u32,
     vm: mmu::Vm,
@@ -729,8 +726,7 @@ impl HeapAllocator {
     pub(crate) fn new(
         dev: &AsahiDevice,
         vm: &mmu::Vm,
-        start: u64,
-        end: u64,
+        range: Range<u64>,
         min_align: usize,
         prot: u32,
         block_size: usize,
@@ -757,14 +753,13 @@ impl HeapAllocator {
             total_garbage: 0,
         };
 
-        let mm = mm::Allocator::new(start, end - start + 1, inner)?;
+        let mm = mm::Allocator::new(range.start, range.range(), inner)?;
 
         Ok(HeapAllocator {
             dev: dev.into(),
             vm: vm.clone(),
-            start,
-            end,
-            top: start,
+            top: range.start,
+            range,
             prot,
             min_align,
             block_size: block_size.max(min_align),
@@ -792,7 +787,7 @@ impl HeapAllocator {
             size_aligned,
         );
 
-        if self.top.saturating_add(size_aligned as u64) >= self.end {
+        if self.top.saturating_add(size_aligned as u64) > self.range.end {
             dev_err!(
                 &self.dev,
                 "HeapAllocator[{}]::add_block: Exhausted VA space\n",
@@ -875,7 +870,7 @@ impl HeapAllocator {
             &self.dev,
             "{} Heap: grow to {} bytes\n",
             &*self.name,
-            self.top - self.start
+            self.top - self.range.start
         );
 
         Ok(())
diff --git a/drivers/gpu/drm/asahi/file.rs b/drivers/gpu/drm/asahi/file.rs
@@ -316,8 +316,7 @@ impl File {
         let ualloc = Arc::pin_init(Mutex::new(alloc::DefaultAllocator::new(
             device,
             &vm,
-            VM_DRV_GPU_START,
-            VM_DRV_GPU_END,
+            VM_DRV_GPU_START..VM_DRV_GPU_END,
             buffer::PAGE_SIZE,
             mmu::PROT_GPU_SHARED_RW,
             512 * 1024,
@@ -328,8 +327,7 @@ impl File {
         let ualloc_priv = Arc::pin_init(Mutex::new(alloc::DefaultAllocator::new(
             device,
             &vm,
-            VM_DRV_GPUFW_START,
-            VM_DRV_GPUFW_END,
+            VM_DRV_GPUFW_START..VM_DRV_GPUFW_END,
             buffer::PAGE_SIZE,
             mmu::PROT_GPU_FW_PRIV_RW,
             64 * 1024,
diff --git a/drivers/gpu/drm/asahi/gem.rs b/drivers/gpu/drm/asahi/gem.rs
@@ -16,6 +16,7 @@ use kernel::{
 
 use kernel::drm::gem::BaseObject;
 
+use core::ops::Range;
 use core::sync::atomic::{AtomicU64, Ordering};
 
 use crate::{debug::*, driver::AsahiDevice, file, file::DrmFile, mmu, util::*};
@@ -76,8 +77,7 @@ impl ObjectRef {
     pub(crate) fn map_into_range(
         &mut self,
         vm: &crate::mmu::Vm,
-        start: u64,
-        end: u64,
+        range: Range<u64>,
         alignment: u64,
         prot: u32,
         guard: bool,
@@ -88,15 +88,7 @@ impl ObjectRef {
             return Err(EINVAL);
         }
 
-        vm.map_in_range(
-            self.gem.size(),
-            &self.gem,
-            alignment,
-            start,
-            end,
-            prot,
-            guard,
-        )
+        vm.map_in_range(self.gem.size(), &self.gem, alignment, range, prot, guard)
     }
 
     /// Maps an object into a given `Vm` at a specific address.
diff --git a/drivers/gpu/drm/asahi/gpu.rs b/drivers/gpu/drm/asahi/gpu.rs
@@ -12,6 +12,7 @@
 //! itself with version dependence.
 
 use core::any::Any;
+use core::ops::Range;
 use core::sync::atomic::{AtomicBool, AtomicU64, Ordering};
 use core::time::Duration;
 
@@ -69,33 +70,19 @@ const DOORBELL_DEVCTRL: u64 = 0x11;
 
 // Upper kernel half VA address ranges.
 /// Private (cached) firmware structure VA range base.
-const IOVA_KERN_PRIV_BASE: u64 = 0xffffffa000000000;
-/// Private (cached) firmware structure VA range top.
-const IOVA_KERN_PRIV_TOP: u64 = 0xffffffa5ffffffff;
+const IOVA_KERN_PRIV_RANGE: Range<u64> = 0xffffffa000000000..0xffffffa600000000;
 /// Private (cached) GPU-RO firmware structure VA range base.
-const IOVA_KERN_GPU_RO_BASE: u64 = 0xffffffa600000000;
-/// Private (cached) GPU-RO firmware structure VA range top.
-const IOVA_KERN_GPU_RO_TOP: u64 = 0xffffffa7ffffffff;
+const IOVA_KERN_GPU_RO_RANGE: Range<u64> = 0xffffffa600000000..0xffffffa800000000;
 /// Shared (uncached) firmware structure VA range base.
-const IOVA_KERN_SHARED_BASE: u64 = 0xffffffa800000000;
-/// Shared (uncached) firmware structure VA range top.
-const IOVA_KERN_SHARED_TOP: u64 = 0xffffffa9ffffffff;
+const IOVA_KERN_SHARED_RANGE: Range<u64> = 0xffffffa800000000..0xffffffaa00000000;
 /// Shared (uncached) read-only firmware structure VA range base.
-const IOVA_KERN_SHARED_RO_BASE: u64 = 0xffffffaa00000000;
-/// Shared (uncached) read-only firmware structure VA range top.
-const IOVA_KERN_SHARED_RO_TOP: u64 = 0xffffffabffffffff;
+const IOVA_KERN_SHARED_RO_RANGE: Range<u64> = 0xffffffaa00000000..0xffffffac00000000;
 /// GPU/FW shared structure VA range base.
-const IOVA_KERN_GPU_BASE: u64 = 0xffffffac00000000;
-/// GPU/FW shared structure VA range top.
-const IOVA_KERN_GPU_TOP: u64 = 0xffffffadffffffff;
+const IOVA_KERN_GPU_RANGE: Range<u64> = 0xffffffac00000000..0xffffffae00000000;
 /// GPU/FW shared structure VA range base.
-const IOVA_KERN_RTKIT_BASE: u64 = 0xffffffae00000000;
-/// GPU/FW shared structure VA range top.
-const IOVA_KERN_RTKIT_TOP: u64 = 0xffffffae0fffffff;
+const IOVA_KERN_RTKIT_RANGE: Range<u64> = 0xffffffae00000000..0xffffffae10000000;
 /// FW MMIO VA range base.
-const IOVA_KERN_MMIO_BASE: u64 = 0xffffffaf00000000;
-/// FW MMIO VA range top.
-const IOVA_KERN_MMIO_TOP: u64 = 0xffffffafffffffff;
+const IOVA_KERN_MMIO_RANGE: Range<u64> = 0xffffffaf00000000..0xffffffb000000000;
 
 /// GPU/FW buffer manager control address (context 0 low)
 pub(crate) const IOVA_KERN_GPU_BUFMGR_LOW: u64 = 0x20_0000_0000;
@@ -355,8 +342,7 @@ impl rtkit::Operations for GpuManager::ver {
         obj.vmap()?;
         let mapping = obj.map_into_range(
             data.uat.kernel_vm(),
-            IOVA_KERN_RTKIT_BASE,
-            IOVA_KERN_RTKIT_TOP,
+            IOVA_KERN_RTKIT_RANGE,
             mmu::UAT_PGSZ as u64,
             mmu::PROT_FW_SHARED_RW,
             true,
@@ -382,8 +368,7 @@ impl GpuManager::ver {
             private: alloc::DefaultAllocator::new(
                 dev,
                 uat.kernel_vm(),
-                IOVA_KERN_PRIV_BASE,
-                IOVA_KERN_PRIV_TOP,
+                IOVA_KERN_PRIV_RANGE,
                 0x80,
                 mmu::PROT_FW_PRIV_RW,
                 1024 * 1024,
@@ -394,8 +379,7 @@ impl GpuManager::ver {
             shared: alloc::DefaultAllocator::new(
                 dev,
                 uat.kernel_vm(),
-                IOVA_KERN_SHARED_BASE,
-                IOVA_KERN_SHARED_TOP,
+                IOVA_KERN_SHARED_RANGE,
                 0x80,
                 mmu::PROT_FW_SHARED_RW,
                 1024 * 1024,
@@ -406,8 +390,7 @@ impl GpuManager::ver {
             shared_ro: alloc::DefaultAllocator::new(
                 dev,
                 uat.kernel_vm(),
-                IOVA_KERN_SHARED_RO_BASE,
-                IOVA_KERN_SHARED_RO_TOP,
+                IOVA_KERN_SHARED_RO_RANGE,
                 0x80,
                 mmu::PROT_FW_SHARED_RO,
                 64 * 1024,
@@ -418,8 +401,7 @@ impl GpuManager::ver {
             gpu: alloc::DefaultAllocator::new(
                 dev,
                 uat.kernel_vm(),
-                IOVA_KERN_GPU_BASE,
-                IOVA_KERN_GPU_TOP,
+                IOVA_KERN_GPU_RANGE,
                 0x80,
                 mmu::PROT_GPU_FW_SHARED_RW,
                 64 * 1024,
@@ -430,8 +412,7 @@ impl GpuManager::ver {
             gpu_ro: alloc::DefaultAllocator::new(
                 dev,
                 uat.kernel_vm(),
-                IOVA_KERN_GPU_RO_BASE,
-                IOVA_KERN_GPU_RO_TOP,
+                IOVA_KERN_GPU_RO_RANGE,
                 0x80,
                 mmu::PROT_GPU_RO_FW_PRIV_RW,
                 1024 * 1024,
@@ -590,7 +571,7 @@ impl GpuManager::ver {
         let addr = *next_ref;
         let next = addr + (size + mmu::UAT_PGSZ) as u64;
 
-        assert!(next - 1 <= IOVA_KERN_MMIO_TOP);
+        assert!(next <= IOVA_KERN_MMIO_RANGE.end);
 
         *next_ref = next;
 
@@ -687,7 +668,7 @@ impl GpuManager::ver {
             initdata: *initdata,
             uat: *uat,
             io_mappings: Vec::new(),
-            next_mmio_iova: IOVA_KERN_MMIO_BASE,
+            next_mmio_iova: IOVA_KERN_MMIO_RANGE.start,
             rtkit <- Mutex::new_named(None, c_str!("rtkit")),
             crashed: AtomicBool::new(false),
             event_manager,
diff --git a/drivers/gpu/drm/asahi/mmu.rs b/drivers/gpu/drm/asahi/mmu.rs
@@ -1069,8 +1069,7 @@ impl Vm {
         size: usize,
         gem: &gem::Object,
         alignment: u64,
-        start: u64,
-        end: u64,
+        range: Range<u64>,
         prot: u32,
         guard: bool,
     ) -> Result<KernelMapping> {
@@ -1096,8 +1095,8 @@ impl Vm {
             (size + if guard { UAT_PGSZ } else { 0 }) as u64, // Add guard page
             alignment,
             0,
-            start,
-            end,
+            range.start,
+            range.end,
             mm::InsertMode::Best,
         )?;
 
