@@ -405,6 +405,70 @@ struct drm_asahi_cmd_render {
405405 __u32 isp_bgobjvals ;
406406};
407407
408+ #define ASAHI_RENDER_UNK_UNK1 (1UL << 0)
409+ #define ASAHI_RENDER_UNK_SET_TILE_CONFIG (1UL << 1)
410+ #define ASAHI_RENDER_UNK_SET_UTILE_CONFIG (1UL << 2)
411+ #define ASAHI_RENDER_UNK_SET_AUX_FB_UNK (1UL << 3)
412+ #define ASAHI_RENDER_UNK_SET_G14_UNK (1UL << 4)
413+
414+ #define ASAHI_RENDER_UNK_SET_FRG_UNK_140 (1UL << 20)
415+ #define ASAHI_RENDER_UNK_SET_FRG_UNK_158 (1UL << 21)
416+ #define ASAHI_RENDER_UNK_SET_FRG_TILECFG (1UL << 22)
417+ #define ASAHI_RENDER_UNK_SET_LOAD_BGOBJVALS (1UL << 23)
418+ #define ASAHI_RENDER_UNK_SET_FRG_UNK_38 (1UL << 24)
419+ #define ASAHI_RENDER_UNK_SET_FRG_UNK_3C (1UL << 25)
420+ #define ASAHI_RENDER_UNK_SET_FRG_UNK_40 (1UL << 26)
421+ #define ASAHI_RENDER_UNK_SET_RELOAD_ZLSCTRL (1UL << 27)
422+ #define ASAHI_RENDER_UNK_SET_UNK_BUF_10 (1UL << 28)
423+ #define ASAHI_RENDER_UNK_SET_FRG_UNK_MASK (1UL << 29)
424+
425+ #define ASAHI_RENDER_UNK_SET_IOGPU_UNK54 (1UL << 40)
426+ #define ASAHI_RENDER_UNK_SET_IOGPU_UNK56 (1UL << 41)
427+ #define ASAHI_RENDER_UNK_SET_TILING_CONTROL (1UL << 42)
428+ #define ASAHI_RENDER_UNK_SET_TILING_CONTROL_2 (1UL << 43)
429+ #define ASAHI_RENDER_UNK_SET_VTX_UNK_F0 (1UL << 44)
430+ #define ASAHI_RENDER_UNK_SET_VTX_UNK_F8 (1UL << 45)
431+ #define ASAHI_RENDER_UNK_SET_VTX_UNK_118 (1UL << 46)
432+ #define ASAHI_RENDER_UNK_SET_VTX_UNK_MASK (1UL << 47)
433+
434+ #define ASAHI_RENDER_EXT_UNKNOWNS 0xff00
435+
436+ /* XXX: Do not upstream this struct */
437+ struct drm_asahi_cmd_render_unknowns {
438+ /** @type: Type ID of this extension */
439+ __u32 type ;
440+ __u32 pad ;
441+ /** @next: Pointer to the next extension struct, if any */
442+ __u64 next ;
443+
444+ __u64 flags ;
445+
446+ __u64 tile_config ;
447+ __u64 utile_config ;
448+
449+ __u64 aux_fb_unk ;
450+ __u64 g14_unk ;
451+ __u64 frg_unk_140 ;
452+ __u64 frg_unk_158 ;
453+ __u64 frg_tilecfg ;
454+ __u64 load_bgobjvals ;
455+ __u64 frg_unk_38 ;
456+ __u64 frg_unk_3c ;
457+ __u64 frg_unk_40 ;
458+ __u64 reload_zlsctrl ;
459+ __u64 unk_buf_10 ;
460+ __u64 frg_unk_mask ;
461+
462+ __u64 iogpu_unk54 ;
463+ __u64 iogpu_unk56 ;
464+ __u64 tiling_control ;
465+ __u64 tiling_control_2 ;
466+ __u64 vtx_unk_f0 ;
467+ __u64 vtx_unk_f8 ;
468+ __u64 vtx_unk_118 ;
469+ __u64 vtx_unk_mask ;
470+ };
471+
408472struct drm_asahi_cmd_compute {
409473 __u64 flags ;
410474
@@ -415,10 +479,10 @@ struct drm_asahi_cmd_compute {
415479 __u32 attachment_count ;
416480 __u32 pad ;
417481
418- __u64 buffer_descriptor ;
482+ __u64 helper_arg ;
419483
420484 __u32 buffer_descriptor_size ; /* ? */
421- __u32 ctx_switch_prog ;
485+ __u32 helper_program ;
422486
423487 __u32 encoder_id ;
424488 __u32 cmd_id ;
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