ASoC: cs42l84: Do not enable the PLL before the clocks are ready

Enabling the PLL with no valid input clock leads to PLL errors. Don't do
that, always disable the PLL before reconfiguring it and let unmute take
care of enabling the PLL.

Also monitor the PLL error bit and complain if it's set.

Signed-off-by: Hector Martin <[email protected]>

Author: marcan

sound/soc/codecs/cs42l84.c

@@ -433,6 +433,8 @@ static int cs42l84_pll_config(struct snd_soc_component *component)
 		break;
 	}
 
+	snd_soc_component_update_bits(component, CS42L84_PLL_CTL1, CS42L84_PLL_CTL1_EN, 0);
+
 	if (pll_ratio_table[i].mclk_src_sel) {
 		/* Configure PLL */
 		snd_soc_component_update_bits(component,
@@ -456,10 +458,6 @@ static int cs42l84_pll_config(struct snd_soc_component *component)
 		snd_soc_component_write(component,
 			CS42L84_PLL_DIVOUT,
 			pll_ratio_table[i].pll_divout);
-
-		snd_soc_component_update_bits(component,
-			CS42L84_PLL_CTL1, CS42L84_PLL_CTL1_EN,
-			CS42L84_PLL_CTL1_EN);
 	}
 
 	return 0;
@@ -633,6 +631,9 @@ static int cs42l84_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
 				if (ret < 0)
 					dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
 
+				if (regval & CS42L84_PLL_LOCK_STATUS_ERROR)
+					dev_warn(component->dev, "PLL lock error\n");
+
 				/* PLL must be running to drive glitchless switch logic */
 				snd_soc_component_update_bits(component,
 					CS42L84_CCM_CTL1,

sound/soc/codecs/cs42l84.h

@@ -31,6 +31,7 @@
 #define CS42L84_TSRS_PLUG_VAL_MASK		GENMASK(3, 0)
 #define CS42L84_PLL_LOCK_STATUS			0x040e // probably bit 0x10
 #define CS42L84_PLL_LOCK_STATUS_LOCKED		BIT(4)
+#define CS42L84_PLL_LOCK_STATUS_ERROR		BIT(5)
 
 #define CS42L84_PLUG				3
 #define CS42L84_UNPLUG				0